1. Field of the Invention
The present invention relates to a data processing system and, particularly, to a microprogram-controlled data processing system incorporating an instruction decoder and multiple register sets, the system being suitable for constructing a microcomputer.
2. Description of the Related Art
Recent advanced micro-miniaturizing technology in the field of semiconductor devices, particularly MOS (Metal Oxide Semiconductor) devices has enabled upgraded functions and performance of microcomputers. In order to avoid the complexity of logics resulting from the enhanced circuit integration, the achievement of an integrated circuit by an orderly structured logic-circuit is becoming the mainstream method. One practice is the microprogram control system. A microprogram-controlled data processing system is generally constructed using an instruction decoder which generates the microprogram ROM address from the instruction word. However, this system necessitates a large scale hardware for the instruction decoder. A microprogram control system coping with this problem by elimination of the instruction decoder is proposed in Japanese Patent Unexamined Publication No. 57-203141. However, this system sets the instruction word directly in part of-the microprogram ROM address information, and therefore as the instruction word length increases from 8 bits to 16 bits and to 32 bits the length of the microprogram ROM address increases with it, resulting disadvantageously in an expanded microprogram ROM address decoder.
Another hardware scheme for upgrading the performance of microcomputers is the general-purpose register system, in which a microcomputer is provided with many registers so that various operations take place among the registers with the intention of high-speed processing. However, if the program includes frequent task switching such as procedures of call/return, the contents of the general-purpose registers need to be saved and output to/from the stack (a first-in-last-out memory) frequently at each switching in order to resume operations. The time used for the saving and resuming operations increases the total processing time, and the increase is the speed of processing is not possible. The time used for the saving and resuming operations is enormous for a system having a large number of general-purpose registers.
As a means for overcoming the problem, there has been proposed the multiple register sets system, in which a plurality of register sets are provided and a register set is used for each task by switching, as described in IEEE MICRO, Vol. 2, No. 4, p. 13, Nov. 1982. This system allows for avoidance of operations for saving the register contents at each procedure call and also for the restoring of original parameter at each procedure return. Moreover, this system does not require transactions of a parameter among procedures, and as a result high-speed register saving/resuming processing can be accomplished. On the other hand, however, only a small part of many register sets is used by application programs with the result of inefficient use of the hardware resources. In addition, the number of registers used for parameter transaction among procedures and the number of registers without connection among procedures are each fixed. Thus, processing, for example, of a procedure requiring an extremely large number of the latter-type registers will be forced to use a memory area even though many of the former-type registers are left unused. Accordingly, this system also has the problem of insufficient use of the hardware resources.